Parasitic Capacitance and Parasitic Inductance of Via

1. Via

Vias are one of the important components of multilayer PCBs, and the cost of drilling usually accounts for 30% to 40% of the cost of PCB manufacturing. Simply put, every hole on the PCB can be called a via. From the perspective of function, vias can be divided into two categories: one is used for electrical connection between layers; the other is used for fixing or positioning of devices. In terms of process, these vias are generally divided into three categories, namely blind vias, buried vias and through vias. Blind holes are located on the top and bottom surfaces of the printed circuit board and have a certain depth for the connection between the surface circuit and the underlying inner circuit. The depth of the hole usually does not exceed a certain ratio (aperture). Buried holes refer to connection holes located in the inner layer of the printed circuit board, which do not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board. Before lamination, the through-hole forming process is used to complete, and several inner layers may be overlapped during the formation of the through-hole. The third type is called a through hole, which passes through the entire circuit board and can be used to realize internal interconnection or as a mounting positioning hole for components. Since the through hole is easier to realize in the process and the cost is lower, most printed circuit boards use it instead of the other two types of vias. The vias mentioned below, unless otherwise specified, are considered as vias. From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole, as shown in the figure below. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, the designer always hopes that the smaller the via hole, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, the smaller the parasitic capacitance of itself. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction in hole size also brings about an increase in cost, and the size of the via hole cannot be reduced indefinitely. It is limited by the technology of drilling and plating: the smaller the hole, the easier it is to drill The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it is impossible to ensure that the hole wall can be evenly plated with copper. For example, the thickness (through-hole depth) of a normal 6-layer PCB board is about 50Mil, so the drilling diameter that PCB manufacturers can provide is as small as 8Mil.

Second, the parasitic capacitance of the via

The hole itself has a parasitic capacitance to the ground. If it is known that the diameter of the isolation hole on the ground layer is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε , the parasitic capacitance of the via hole is approximately: C=1.41εTD1/(D2-D1) The main impact of the parasitic capacitance of the via hole on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit. For example, for a PCB board with a thickness of 50Mil, if a via hole with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, then we can approximate the via hole by the above formula The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, and the rise time variation caused by this part of capacitance is: T10-90=2.2C(Z0/2)=2.2 x0.517x(55/2)=31.28ps. From these values, it can be seen that although the effect of slowing the rising delay caused by the parasitic capacitance of a single via is not obvious, if the via is used multiple times in the wiring to switch between layers, the designer still needs to consider it carefully.

3. Parasitic inductance of vias

Similarly, there is parasitic inductance as well as parasitic capacitance in the via hole. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of the via hole is often greater than the influence of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can use the following formula to simply calculate the approximate parasitic inductance of a via: () - PCB Design Guidelines - About Vias where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center drilled hole. It can be seen from the formula that the diameter of the via hole has little influence on the inductance, but the length of the via hole has a great influence on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010) 1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when there is a high-frequency current passing through. In particular, it should be noted that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so that the parasitic inductance of the vias will double. 4. Via design in high-speed PCB Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. effect.

In order to reduce the adverse effects brought by the parasitic effects of vias, we can try our best in the design:

1. Considering both cost and signal quality, select a reasonable via hole size. For example, for 6-10 layers of memory module PCB design, it is better to use 10/20Mil (drilling/pad) vias. For some high-density and small-sized boards, you can also try to use 8/18Mil vias. hole. Under the current technical conditions, it is difficult to use smaller-sized vias. For power or ground vias, consider using a larger size to reduce impedance.

2. From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reduce the two parasitic parameters of the via.

3. Try not to change the layer of the signal traces on the PCB, that is to say, try not to use unnecessary vias.

4. The pins of the power supply and the ground should be drilled via holes nearby. The shorter the leads between the via holes and the pins, the better, because they will increase the inductance. At the same time, the leads of power and ground should be as thick as possible to reduce impedance.

5. Place some grounded vias near the vias where the signal changes layers to provide a close loop for the signal. It is even possible to place a large number of redundant ground vias on the PCB. Of course, there is a need for flexibility in design. The via model discussed above is the case where each layer has a pad, and sometimes, we can reduce or even remove the pads of some layers. Especially in the case of a very large via hole density, it may cause a broken slot that isolates the loop on the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.